1. Field of the Invention
This application relates to amplifiers and more particularly to amplifier topologies providing high DC gain.
2. Description of the Related Art
Amplifiers are an essential component in many analog circuits, and often set the bottleneck for the dynamic and noise performance of such systems. An example system for which an amplifier plays a key role is a switched capacitor network used within a pipelined analog-to-digital converter (ADC). FIG. 1A illustrates a high level block diagram of one stage of a pipelined ADC. The input voltage Vin is sampled in sample and hold circuit 101. The input voltage is also supplied to analog-to-digital converter (ADC) 103, which converts the voltage to an “M” bit digital representation. M may be e.g., one bit or several bits. The M bit(s) are supplied to a combiner block (not shown) and also to a digital-to-analog converter (DAC) 105, which converts the M bit representation to an analog value. That analog voltage is then subtracted from the input voltage in the summing circuit 107 and the residue after the subtraction is amplified in amplifier 109 and supplied to the next stage in the pipelined ADC.
FIG. 1B illustrates a high level diagram of a pipelined ADC showing various stages of the pipelined ADC and the digital combiner block 121 that combines the digital outputs of the various stages. FIG. 1C shows an embodiment of a switched capacitor network that may be used in each stage 100 to sample the voltage input to the stage (Vin), subtract a quantized representation of that sampled value (αVref) and then amplify the residue. In the example shown in FIG. 1C, M=1 and a is +1 or −1 for M=1 and α is set according to a separate ADC that feeds the DAC as shown in FIG. 1A. If M>1, then the ADC may be modeled as one capacitor (as in FIG. 1C) with α having values between −1 and 1. In FIG. 1C, Cf is the feedback capacitor, Cs is the sample capacitor, Cpar is parasitic capacitance, CL is load capacitance. Amplifier 109 receives the residue input Vm (where “m” is minus to reflect the inverting nature of the amplifier) and Vcm is the common mode input (assumes a single-ended system, as is shown). The clock signals Φ1, Φ1p, and Φ2 control the switches of the switched capacitor network in non-overlapping manner to configure the network for sampling as shown at 131 or to configure the network to amplify the residue as shown at 133. Clock signal Φ1p drives the auto-zero switches. Key performance issues of such an amplifier are the signal-to-noise ratio (SNR) and linearity that it achieves in amplifying the residue. To achieve high SNR, it is beneficial to achieve a wide output swing of the amplifier. However, it is challenging to maintain high linearity with a wide output swing, so that a trade-off often exists in achieving excellent SNR versus linearity performance.
To improve linearity while maintaining good SNR, it is highly desirable to achieve a large DC gain for the amplifier. FIG. 2 shows a basic common source amplifier along with a calculation of its DC gain. A key metric for determining such DC gain is the product of the transistor transconductance, gm, and its output resistance, ro. This gmro product is referred to as the intrinsic gain of the transistor device, and it is desirable that gmro have a large value in order to achieve large DC gain for the amplifier. Assuming that the amplifier is implemented with CMOS transistors, an important trend to consider is that advanced CMOS fabrication technologies often offer low values of gmro, which creates challenges in achieving high DC gain of amplifiers in such processes. The term rop in FIG. 2 refers to output resistance associated with the PMOS device 201 and ron to output resistance associated the NMOS device 203.
To further improve DC gain of an amplifier beyond what is offered by the basic common source structure, topological changes can be made to the amplifier. As indicated in FIG. 2, the most common approaches for such DC gain boosting are to utilize multiple amplifier stages, cascoding of transistors, and cascode-based gain enhancement. Most modern amplifiers used within pipeline ADCs leverage a combination of these techniques to achieve high DC gain. Note that compensation to achieve stability of multiple gain stages in feedback gets complicated with more than two stages.
FIG. 3 shows a folded cascode amplifier which is commonly used within pipeline ADCs. The technique of cascode-based gain enhancement in FIG. 3 is leveraged to achieve high DC gain and acceptable output swing. Unfortunately, while this topology has been very effectively used in older CMOS fabrication processes such as 180 nm CMOS, it suffers from insufficient DC gain and output swing in more modern processes such as 55 nm CMOS due to the relatively low gmro and low voltage supply encountered with such processes. In general, cascode-based gain enhancement suffers under low supply voltage constraints as encountered with modern CMOS processes.
Accordingly, improvements in amplifier topologies to provide DC gain enhancement with wide output swing is desirable.